Semiconductor memory devices continue to play important roles in computing systems, as both standalone components, or as memory arrays "embedded" into a larger integrated circuit. The basic functions of memory devices are well-known; data is read from or written into the device (or the device is programmed) by the application of an address, in conjunction with various control signals. In order to accommodate faster system speeds, it is desirable to make memory devices with as fast an operating speed as possible. At the same time, it is also desirable to make semiconductor memory devices as small as possible. Smaller memory devices can be typically manufactured on a more cost effective basis.
Advances in manufacturing allow generational "shrinks" in memory device features, and thus allow the production of devices having smaller overall sizes. However, such approaches utilize existing memory device layout approaches, and so only provide incremental reductions in device sizes.
Another important feature of a memory device is whether the memory device is volatile or nonvolatile. Volatile memory devices are generally preferred for their faster operating speeds. Reading information from, and writing information to, requires only a very small amount of time. The disadvantage of volatile memory devices is that once power is removed from the device, the information stored within is lost. In contrast, nonvolatile memory devices can retain data in the absence of power. A common drawback to most nonvolatile memory devices is their relatively slow access speeds. In addition, some nonvolatile memory devices, such as electrically erasable programmable read only memories (EEPROMs), require a programming operation in order to initially store data within the memory devices. Such programming operations can be complex, and require relatively long periods of time, and consume large amounts of power.
One type of memory device which provides both nonvolatile storage and relatively rapid operating speeds, is the ferroelectric random access memory (FeRAM or FRAM). A FeRAM typically utilizes capacitor structures having a dielectric formed from a ferroelectric material. Ferroelectric capacitors exhibit a hysteresis (or inelastic) response to an applied electric field. That is, in a standard (i.e., non-ferroelectric capacitor) when an electric field is applied, positive charge is displaced toward one plate of the capacitor, while negative charge is displaced toward an opposite plate. The displacement of charge is often referred to as polarization. Once the electric field is returned to zero, the charges return to their original distribution. Unlike conventional capacitors, in ferroelectric capacitors, a certain amount of charge displaced by an initial electric field, will remain displaced, and not return to a nonpolarized state once the field is removed. An opposite field will then be required to place the ferroelectric capacitor back into the non-polarized state.
A common FeRAM cell, is the one-transistor, one capacitor memory cell. Such memory cells provide for a compact cell size. Within a FeRAM memory device, the FeRAM cells are arranged into an array of rows and columns. The memory cells within an array are accessed by word lines, bit lines, and plate lines within the array. The manner in which memory cells are coupled to their respective word lines, bit lines and plate lines (the array "architecture") can affect the performance and overall resulting size of a FeRAM. Thus, array architecture can have a considerable impact in determining overall memory device size.
U.S. Pat. No. 5,541,872 sets forth a FeRAM that utilizes one-transistor, one-capacitor memory cells. The FeRAM array and associated sense amplifiers are reproduced in a schematic diagram in FIG. 1. The prior art FeRAM is designated by the general reference character 100 and is shown to include a number of memory cells, shown as 102a-102e. Each memory cell 102a-102e includes an n-channel pass transistor N100a-N100e and an associated ferroelectric capacitor C100a-C100e. Each ferroelectric capacitor is connected by a first plate to the pass transistor of its associated memory cell.
Memory cells 102a, 102c and 102e are within a first row, and have the gates of their respective access transistors (N100a, N100c and N100e) coupled to a first word line 104a (WL1). The second plates of the ferroelectric capacitors within the row (C100a, C100c and C100e) are coupled to a first plate line 106a. Memory cells 102b and 102d are in a second row, and are coupled to a second word line 104b (WL2). The second plate of ferroelectric capacitors C100b and C100d are coupled to a second plate line 106b. The memory cells (102a-102e) are each coupled to a given bit line (108a-108e) at the sources of their respective pass transistors (N100a-N100e).
The prior art FeRAM of FIG. 1 sets forth a "folded" bit line architecture. In a folded bit line architecture, the activation of a word line results in memory cell data being coupled to alternating bit lines. For example, in FIG. 1, when word line 104a is activated (goes high), memory cells 102a, 102c and 102e are coupled to bit lines 108a, 108c and 108e (which can be considered odd bit lines). The remaining bit lines 108b and 108d (which can be considered even bit lines) are equalized to a reference voltage. Pairs of adjacent bit lines, each consisting of an even bit line and an odd bit line, are coupled to a sense amplifier. Thus, as shown in FIG. 1, bit lines 108b and 108c are coupled to a sense amplifier 110a, while bit lines 108d and 108e are coupled to sense amplifier 110b. Folded bit line architectures provide the advantage of increased noise resistance, as the arrangement of the bit line pairs results in greater rejection of common mode noise.
A drawback to prior art folded bit line architectures is the amount of area required for the memory cells of the array. Referring now to FIG. 2, a top plan view of a folded bit line FeRAM array, such as that of FIG. 1, is set forth. The FeRAM array is designated by the general reference character 200 and is shown to be formed on a semiconductor substrate 202 having a number of active areas (204a-204h) formed therein. The active areas (204a-204h) are separated from one another by isolation structures 206.
A number of word lines 208a-208f are formed over the active areas (204a-204h). The active areas (204a-204h) can be considered to be grouped into even columns and odd columns. In the folded bit line arrangement of FIG. 2, consecutive word line pairs cross over the active areas of odd columns or even columns. For example, word line pair 208a/208b crosses over active areas 204a, 204d and 204g, which can be considered to be in even columns. Word line pair 208c/208d crosses over active areas 204c and 204f, which can be considered to be in odd columns. Coupled to each active area are two storage node contacts and one bit line contact. The storage node contacts for active area 204h are shown as items 210, and the bit line contact is shown as item 212. The storage node contacts and bit line contacts for the other active areas (204a-204g) are illustrated in FIG. 2, but not given a reference character.
It is understood that bit line contacts are coupled to bit lines (not shown in FIG. 2) which would be disposed in the column direction. Each storage node contact is coupled to one plate of a ferroelectric capacitor (also not shown in FIG. 2).
The areas occupied by the memory cells of the array 200 are shown in FIG. 2 by area indication 214. If the minimum manufacturable feature size (for example the width of a word line) is given as "F," the memory cells are shown to occupy an area equal to 8F.sup.2. While generational shrinks in such folded bit line architectures can result in smaller memory device sizes, it would be desirable to find some way of further reducing the size of the FeRAM device.
Smaller FeRAM memory cell areas are possible, but can suffer in performance. For example "open" bit line architectures can memory cells having areas that are smaller than those of folded bit line architectures, but will suffer more from the effects of noise. An open bit line array arrangement is set forth in FIG. 3. The open bit line array is designated by the general reference character 300, and includes a number of active areas 302a-302j formed in a semiconductor substrate 304. The active areas 302a-302j each include two storage node contacts and one bit line contact. Word lines (306a-306d) are formed over the active areas (302a-302j). Unlike the folded bit line arrangement of FIG. 2, in the open bit line arrangement, each word line overlaps an active area in each column.
In the open bit line case of FIG. 3, the area of one memory cell is shown by a cell area 306. If a minimum feature size is given as F, the area consumed by a memory cell in an open bit line arrangement is shown to be 6F.sup.2. Thus, while an open bit line arrangement provides for smaller memory cell areas, it is recalled that such arrangements are susceptible to noise.
It would be desirable to find some way of reducing the physical size of a ferroelectric memory device array, without incurring the drawbacks of the prior art.